Technology

How flat is a flat on the road to a small transistor?

Transistors are the building blocks of modern electronic devices used in everything from televisions to laptops. As transistors get smaller and more compact, so do electronic devices. Therefore, a mobile phone is a very powerful computer that fits in the palm of your hand.

But there is a scaling issue. Transistors are currently so small that it is difficult to turn them off. An important device element is the channel through which charge carriers (such as electrons) move between electrodes. If the channel gets too short, quantum effects can effectively jump from one side to the other, even if the electron shouldn’t be there.

One way to overcome this sizing obstacle is to use a layer of 2D material (only one atom thick) as the channel. Atomic thin channels help enable smaller transistors by making it harder for electrons to jump between electrodes. One of the well-known examples of 2D materials is graphene, whose discoverer won the Nobel Prize in Physics in 2010. But there are other 2D materials, and many believe that they are the future of transistors, with channel thicknesses ranging from a few nanometers (nm, one billionth of a meter) to less than a nanometer. Current 3D limits.

Research in this area has exploded, but one problem has always been overlooked, according to a team of scientists from the National Institute of Standards and Technology (NIST), Purdue University, Duke University, and North Carolina State University. rice field. 2D materials and their interfaces (which are intended to be flat when researchers stack each other) may not actually be flat. This non-flatness can have a significant impact on device performance.

In a new study published on April 26, 2022, ACSNano, The research team reports the measurement results of the flatness of these interfaces in transistor devices incorporating 2D materials. They are the first group to take high-resolution microscopic images showing the flatness of these 2D layers in a complete device array on a relatively large scale, as opposed to the more common 10 nm to 100 meters. .. nm range.

Common architecture for traditional MOSFETs and 2D FETs. A FET (Field Effect Transistor) is a device that regulates the flow of charge carriers (electrons, etc.) across a channel that has three terminals: source, drain, and gate. MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are the most widely used type of FETs to date and are the building blocks of modern electronic devices that have been used in commercial electronic devices for over 50 years. One of the main differences between traditional 3D MOSFETs and 2D FET “emerging technologies” is that the channels of traditional MOSFETs are 3D materials, while the channels of 2D FETs are 2D materials.

credit:

Sean Kelly / NIST

Scientists have successfully imaged a series of 2D-2D and 2D-3D interfaces on devices created using a variety of common manufacturing methods. Their results show that assuming that the interface is flat when it is not flat is a much bigger problem than researchers in this field are aware of.

“We are educating the community on issues that have been overlooked,” said Cartrictor of NIST. “It’s hindering the adoption of new materials. The first step in solving a problem is to know that there is a problem.”

Potential benefits include giving the scientific community more control over the manufacture of devices.

“A lack of understanding of the flatness of 2D interfaces is a major obstacle to improving devices based on 2D materials,” said Zhihui Cheng, lead author at NIST and Purdue University at the time of publication. “We have announced a way to quantify flatness to Angstrom resolution, which opens many windows for people to explore tensions and interactions in 2D interfaces.”

Not as flat as I expected

In traditional transistors, the 3D source electrode emits electrons to the 3D drain electrode through the 3D channel. In a 2D transistor, electrons move across the 2D material. The area where these different materials meet is called the interface.

The lack of flatness in these interfaces can cause problems with the current flow of devices that use 2D materials. For example, if there is close physical contact between the source metal and the 2D channel, there is also close electrical contact and the current will flow smoothly. Conversely, the gap between the 2D channel material and the source impairs electrical contact and reduces current flow. (See the “Idealization and Reality” diagram.)

Idealized anti-reality diagram

Researchers generally expect transistors made of 2D crystals to have perfectly flat 2D-2D and 3D-2D interfaces (contact regions). However, new evidence actually shows that there are obvious bends and nanogaps at these interfaces.

credit:

Sean Kelly / NIST

In their paper, researchers described several different types of 2D interfaces, including those made between nickel source and drain electrodes, and 2D channels made from 2D crystalline molybdenum disulfide (MoS). I’m investigating.2), Crystalline hexagonal boron nitride (hBN), and an encapsulated layer of aluminum oxide.

Scientists typically superimpose 2D and 3D materials on top of each other during the device manufacturing process. For example, researchers may stack 2D materials on pre-patterned metal contacts. However, the researchers found that stacking of this type of 2D material had a significant impact on their flatness, especially near contact areas. MoS occurred when adding hBN2 It deforms up to 10 nm on one side of the contact. The regions away from the contacts tended to be relatively flat, but some of these regions still had a 2-3 nm gap.

While testing the effect of atomic layer deposition (a common technique used to lay a thin layer of material) on the flatness of a 2D interface, the research team found a direct interface between aluminum oxide and MoS. I found.2 More deformed than the interface between hBN and MoS2.. After investigating the flatness of the 3D-2D contact interface, the team found a surprisingly large nanocavity at the interface between the nickel contact and 2D MoS.2 channel.

To connect these non-flat interfaces to real device performance concerns, the team tested the electrical properties of transistors made from these materials. Researchers have found that the non-flatness added to the channel actually has the effect of improving device performance.

“Overall, these results reveal how the structure of the 2D-2D and 2D-3D interfaces depends on the material and manufacturing process,” Cheng said.

To make the observations, the group used a type of high-resolution scanning transmission electron microscopy (scanning TEM) that could decompose the image to the level of a single atom.

“Most of this area is pure research,” Richter said. “People create one or two devices, but there is nothing extra that a microscopist can provide to disassemble.” On the other hand, it was important to create and analyze the devices in this study. ..

“We didn’t do anything special about the measurements,” Richter continued. “But the combination of electrical measurement know-how and high-resolution TEM expertise is not common.”

“By correlating the resolution and record length of the sub-angstrom of the cross-section TEM with the characteristics of the device, our work has broadened and deepened our perspective on the complexity and complexity of 2D interfaces,” Cheng said. I am saying.

Benefits for everyone

Researchers have stated that the application of the study involves reducing unintended variability between devices, and its 2D flatness is an important factor.

Imaging methods also help, ultimately, give scientists more control over manufacturing. In certain processes, the 2D structure is mechanically strained, twisting like a squeezed washcloth, crushing and stretching like an accordion. This can change device performance in unpredictable ways that scientists do not yet fully understand. A better understanding of how strain affects device performance gives researchers more control over this performance.

“Tension is not necessarily a bad thing,” Richter said. “The high-end transistors people are making today have built-in strain to actually make them work better. With 2D materials, the way to do that is not so obvious, but it uses non-flatness. It may be possible to create the required strain. “

The authors hope that their research will inspire new efforts to increase the resolution of 2D interface flatness measurements to the resolution of sub-angstroms.

“We have some preliminary data, but that’s really just the beginning of this study,” Chen said.

–Report and writing by Jennifer Lauren Lee


Paper: Z. Cheng, H. Zhang, ST Le, H. Abuzaid, G. Li, L. Cao, AV Davydov, AD Franklin, and CARichter. Is the 2D interface really flat? ACSNano.. Published April 26, 2022. DOI: 10.1021 / acsnano.1c11493

https://www.nist.gov/news-events/news/2022/06/road-tiny-transistors-how-flat-flat How flat is a flat on the road to a small transistor?

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