Based in the United States, Aldec’s Nevada is a provider of mixed HDL language simulation and hardware-assisted verification of FPGA and ASIC designs, and HES, an ASIC / SoC physical prototyping and hardware emulation board capable of supporting designs of approximately 83M. -VU19PD-ZU7EV is the size of the ASIC gate that was released.
Compared to boards of similar capacity, the HES-VU19PD-ZU7EV uses only two FPGAs to provide the logic. This simplifies FPGA partitioning and reduces launch time for projects designed for medium-sized ASICs or SoCs. For larger designs, four boards can be connected via a high-speed backplane (coming later this year) to provide the equivalent of approximately 332 MASIC gates. Backplanes can also be interconnected (up to 3) to accommodate designs of approximately 996 MASIC gates.
The HES-VU19PD-7U7EV Logic Module FPGAs are both Virtex UltraScale + VU19P devices and are Xilinx’s largest logic capacity FPGAs to date. Aldec’s new HES board also features the Xilinx Zynq UltraScale + ZU7EVMP SoC. It acts as a host module and features a quad-core ARM Cortex-A53, a dual-core ARM Cortex-R5 real-time processing unit, and a PCIe Gen3 embedded IP.
Chris Tinson, Senior Director of the Xilinx Testing, Measurement and Emulation Market, said: “Aldec has incorporated two of these devices and one of the most powerful Zynq FPGAs, creating a highly versatile platform that allows designers to quickly track ASIC and SoC projects.”
Zibi Zalewski, General Manager of Aldec’s Hardware Division, commented: Expand capacity and functionality in both emulation and prototyping scenarios. Also, using a Zynq US + device as a controller means that you can host a test bench for prototyping. In fact, the HES board’s prototyping and emulation capabilities are unique to Aldec. “
Zalewski further indicates that a revision of HES-DVM, a fully automated and scalable hybrid verification environment for Aldec’s SoC and ASIC designs, is underway. He adds: “This unleashes the power of the new board, for example, through enhanced debugging capabilities.”
The HES-VU19PD-7U7EV has PCIe switch devices that provide PCIe x16 Gen 3 connectivity with logic devices and PCIe x8 Gen 3 connectivity with controller FPGAs. Other interfaces include QSFP-DD and Ethernet (1Gb) for each logic FPGA, and USB for the control FPGA.
In terms of memory interface, the new HES board offers 5 SODIMMs (2 for each VU19P, 1 for ZU7EV) to accommodate external DDR4 memory and NVMe M.2 PCIe for additional SSD storage. I will.
The HES-VU19PD-7U7EV comes with Aldec’s HES Proto-AXI software package. This package contains all the drivers and utilities needed to communicate and program with the board. To quickly boot the host connection, Aldec provides a ready-to-use image of embedded Linux for ZU7EV devices.
A HES Proto-AXI solution is available as an optional extra. It is part of the Proto-AXI installer package and comes with technical documentation and design examples.
The new board also features two FMC connectors for interfacing with daughter cards, greatly supporting the development of SoCs for use in a wide range of applications.
The above is the architecture of Aldec’s HES-VU19PD-ZU7EV. This is an ASIC / SoC physical prototyping and hardware emulation board that can accommodate designs with sizes of approximately 83 MASIC gates.
HES prototyping board
HES is a feature-rich family of SoC / ASIC pre-silicon physical prototyping and hardware emulation boards. This family features boards with high-performance devices from either Xilinx (including Xilinx-7, Virtex UltraScale, Virtex UltraScale +, Zynq UltraScale +) or Microchip (PolarFire and SmartFusion2).
The HES high-speed backplane means that the boards can be interconnected and can easily be designed for ASICs or SoCs with multiple 100m ASIC gates. In addition, all boards can be used with Aldec’s FMC daughter card range, which is the widest range in the EDA industry. The HES board can also be used for algorithm acceleration in high performance computing (HPC) applications such as high frequency trading (HFT), computer vision, and genome alignment.
HES-DVM is a fully automated and scalable hybrid verification environment for SoC and ASIC designs. Utilizing the latest co-embroidery standards such as SCE-MI and TLM and the latest FPGA technology, hardware and software design teams have early access to hardware prototypes of their designs. By working with each other at the same time, you can develop and validate high-level code with RTL accuracy and speed-efficient SoC emulation or prototyping models, reducing test time and the risk of silicon respinning.
https://www.electronicsworld.co.uk/aldec-introduces-a-new-hes-board-for-prototyping-and-emulating-medium-to-large-asics-and-socs/32430/ Aldec announces new HES boards for prototyping and emulating medium to large ASICs and SoCs – Electronics World